When ECD Hits the Wall at 10nm, What Will Our Options Be for Copper Fill?

When ECD Hits the Wall at 10nm, What Will Our Options Be for Copper Fill?

Despite the fact that the International Technology Roadmap for Semiconductors (ITRS) has just published its final missive and has shifted efforts to the heterogeneous integration roadmap, developments for smaller technology nodes continue at leading integrated device manufacturers and foundries. According to a SEMI Engineering blog post published in January, we can expect to see 10nm devices ship later this year, and while the path for 7nm seems clear, 5nm is expected to have significant technical and economic challenges.

As the industry transitions to smaller nodes, one of the identified challenges is filling copper (Cu) interconnects. The conventional approach relies on physical vapor deposition (PVD) to deposit the Cu seed layer, followed by electrochemical deposition (ECD) to complete the Cu fill process. For feature sizes below 20nm, the increasing aspect ratio and decreasing width of the trenches make conventional ECD difficult. As a result, voiding can occur, bringing with it the associated yield-hits on high-value logic devices.

A bottom-up fill approach to replace ECD, which has been in development for years but never successfully commercialized, is a combination of PVD with thermal reflow. PVD reflow is used as a way to preferentially thicken the metal at the bottom of a trench or via to prevent void formation inside the feature as filling progresses. The problem is, with PVD reflow, the fill process can only be optimized across a narrow range of feature sizes. As a rule, there is a wide range of critical dimensions and pitches on the wafer, so optimizing PVD reflow for a subset of critical dimensions doesn’t work for features with dimensions outside of that subset, and it creates void defects. Due to these issues, as well as its increased complexity and cost compared with ECD, PVD reflow has never been successful and has never entered production.

Currently, the process of record for Cu deposition is still ECD using acidic chemistry. However, at 10nm, this method is expected to hit the wall. This is where aveni’s approach proves highly beneficial, while using the same industry-standard ECD equipment.

Our Electrografting (eG™) approach utilizes alkaline chemistry, which enables bottom-up filling, thanks to the formation of an ultra-stable polynuclear Cu layer during the early stage of the deposition process. This layer inhibits Cu reduction, leading to a very strong suppressing effect. Bottom-up Cu growth is achieved by means of selective breakdown of the suppressing layer from the bottom to the top of the features without any accelerator additive. aveni’s efficient new plating chemistries and processes produce excellent nucleation, void-free Cu filling, improved line resistance and reduced cost.

Even though Moore’s law may be coming to an end, there is no question that new materials, new processes and new integration schemes are required to propel semiconductor manufacturing to future nodes. An example of this is aveni’s approach to remove the cobalt liner from the Cu dual damascene stack, which is not an option for conventional acidic ECD processes. Cobalt (Co) liner removal creates more wiring “real estate,” because the volume inside the features that was taken up by Co is replaced with Cu. This enables better Cu filling, for improved device performance, lower RC delay, and it effectively postpones the demise of Moore’s law. Rather than dismissing ECD altogether and rushing to embrace a deposition method that is more complex, less reliable and more expensive, we strongly recommend considering aveni’s Electrografting technology and process solutions for advanced Cu fill.

Visit www.aveni.com for more information.

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